1. Field of the Invention
The present invention relates to a manufacturing method for layered chip packages each of which includes a plurality of stacked semiconductor chips.
2. Description of the Related Art
In recent years, lighter weight and higher performance have been demanded of portable devices typified by cellular phones and notebook personal computers. Accordingly, there has been a need for higher integration of electronic components for use in the portable devices. With the development of image- and video-related equipment such as digital cameras and video recorders, semiconductor memories of larger capacity and higher integration have also been demanded.
The yield of chips from a wafer that is to be cut later into a plurality of chips, i.e., the ratio of the number of conforming chips to the total number of chips in the wafer, is generally 90% to 99%. A layered chip package includes a plurality of chips. Therefore, the possibility that all the chips included in a layered chip package are conforming is lower than the yield of the chips. As the number of chips included in a layered chip package increases, the possibility that all the chips included in the layered chip package are conforming decreases.
A case will now be contemplated where a memory device such as a flash memory is constructed using a layered chip package. Generally, in a memory device such as a flash memory, a redundancy technique to replace a defective column of memory cells with a redundant column of memory cells is used so that the memory device can operate normally even when some memory cells are defective. Also in a memory device constructed using a layered chip package, if some of a plurality of memory cells included in a chip are defective, the redundancy technique can be used to allow the memory device to operate normally while allowing the use of the chip including the defective memory cells. Suppose, however, that a chip including a control circuit and a plurality of memory cells becomes defective due to, for example, a wiring failure in the control circuit, and even the redundancy technique cannot allow the chip to operate normally. In such a case, the defective chip is no longer usable. One possible solution to this case is to replace the defective chip with a conforming chip. However, this increases the manufacturing cost of the layered chip package.
U.S. Pat. No. 8,203,215 B2 discloses the technology to configure a main package by stacking a plurality of layer portions that include respective semiconductor chips and to disable defective semiconductor chips by intentionally omitting electrical connection of the defective semiconductor chips to wiring. Further, U.S. Pat. No. 8,203,215 B2 discloses the technology to construct a composite layered chip package by stacking together a main package and an additional portion where the main package includes a defective semiconductor chip. The additional portion includes a conforming semiconductor chip to substitute for the defective semiconductor chip.
This technology provides a composite layered chip package that is capable of providing, even if a defective semiconductor chip is included therein, the same functions as those for the case where no defective semiconductor chip is included. This technology, however, has room for improvement in terms of simplification of the manufacturing process and in terms of manufacturing cost.